Blackfin

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Blackfin refers to a family of 16/32-bit microprocessors with built-in Digital ... Blackfin processors use a 32-bit RISC MCU programming model on a SIMD ...
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Blackfin refers to a family of 16/32-bit microprocessors with built-in Digital Signal Processor (Digital signal processor) functionality, which is traditionally only accompanied by a small and power-efficient microcontroller. The result is a low-power, unified processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real time H264 video encoding.

The processors come in several varieties of hardware development kits and a community supported uClinux is available.Currently the microprocessor is manufactured by Analog Devices.

Architecture Details Blackfin processors use a 32-bit RISC microcontroller unit programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).

The Blackfin processor architecture was announced in December, 2000 and first demonstrated at the Embedded Systems Conference in June, 2001.

The Blackfin architectures takes the best of ADI's older Super Harvard Architecture Single-Chip Computer architecture, and the best of Intel's Xscale architecture and puts them into a single core, combining Digital Signal Processing (DSP) and micro-controller functionality. There are many differences in the core architecture between Blackfin/MSA and Xscale/ARM or SHARC, but the combination provides improvements in performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses a number of different models of CPU, each with advantages for particular applications. The Blackfin family is summarized in the following table.

Analog Devices keeps a comprehensive list of products at this location: {]!!Parallel_Peripheral_Interface!!SDRAM!!USB!!ATAPI!!Controller_Area_Network!!I²C (TWI)!!Serial_Peripheral_Interface_Bus!!UART!!SPORT!!GPIO!!Media Oriented Systems Transport |-|BF542 ||600||1||64 (16)||64 (32)
4||-||-||-||Yes||-||1||1||0||DDR
x16||1||1||1||1||2||3||3||152 pins|| -|-|BF544 ||533||1||64 (16)||64 (32)
4||64||-||Yes||Yes||-||-||1||1||DDR
x16||-||-||2||2||2||3||3||152 pins|| -|-|BF548 ||600||1||64 (16)||64 (32)
4||128||-||Yes||Yes||-||1||1||1||DDR
x16||2.0
OTG||1||2||2||3||4||4||152 pins|| -|-|BF549 ||533||1||64 (16)||64 (32)
4||128||-||Yes||Yes||-||1||1||1||DDR
x16||2.0
OTG||1||2||2||3||4||4||152 pins|| 1|-|BF531 ||400||1||32 (16)||16 (16)
4||-||-||-||-||-||-||1||-||SDR
x16||-||-||-||-||1||1||2||16||-|-|BF532 ||400||1||48 (16)||32 (32)
4||-||-||-||-||-||-||1||-||SDR
x16||-||-||-||-||1||1||2||16||-|-|BF533 ||600||1||80 (16)||64 (32)
4||-||-||-||-||-||-||1||-||SDR
x16||-||-||-||-||1||1||2||16||-|-|BF534 ||500||1||64 (16)||64 (32)
4||-||-||-||-||-||-||1||-||SDR
x16||-||-||1||1||1||1||2||48||-|-|BF536 ||500||1||64 (16)||32 (32)
4||-||-||-||-||1||-||1||-||SDR
x16||-||-||1||1||1||1||2||48||-|-|BF537 ||600||1||64 (16)||64 (32)
4||-||-||-||-||1||-||1||-||SDR
x16||-||-||1||1||1||1||2||48||-|-|BF538 ||500||1||80 (16)||64 (32)
4||-||-||-||-||-||-||1||-||SDR
x16||-||-||1||2||3||3||4||54||-|-|BF538F ||500||1||80 (16)||64 (32)
4||-||512
1024||-||-||-||-||1||-||SDR
x16||-||-||1||2||3||3||4||54||-|-|BF539 ||500||1||80 (16)||64 (32)
4||-||-||-||-||-||-||1||-||SDR
x16||-||-||1||2||3||3||4||38||1|-|BF539F ||500||1||80 (16)||64 (32)
4||-||512
1024||-||-||-||-||1||-||SDR
x16||-||-||1||2||3||3||4||38||1|-|BF561 ||600||2||64 (16)
per core||64 (32)
4
per core||128||-||-||-||-||-||2||-||SDR
x32||-||-||-||-||1||1||2||48||-|-|BF535 ||350||1||16 ||32
4||256||-||-||-||-||-||-||-||SDR
x16||1.1||-||-||-||2||2||2||16||-|-|}

In addition to the features in the table above, all Blackfin processors have the following peripherals

Debug/JTAG Interface for in-system debugging
Real-time clock
Internal core voltage switching regulator
Watchdog timer
Timers/PWM outputs/PWM capture ports
Core timer (runs at core clock speed)

Architecture Features Core Features The heart of the Blackfin depends on the person looking at it.

For some, it is a Digital signal processor. It combines two 16-bit hardware Multiply-accumulates, two 40-bit Arithmetic logic units, and a 40-bit barrel shifter. This allows the processor to execute up to three instructions per clock cycle, depending on the level of Compiler optimization of the compiler (or of the programmer).
For others, it is yet another RISC core. It includes memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The Instruction Set Architecture also features a high level of expressiveness, allowing the assembly programmer (or compiler) to highly optimize an algorithm to the hardware features present.

Memory and DMA The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers all reside in this 32-bit address space.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard_architecture. Instruction memory and data memory are independent and connect to the core via dedicated memory buses which allows for high sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache (independently).

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR FLASH, NAND FLASH and SRAM. Some Blackfin also include mass-storage interfaces such as ATAPI, and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the significant core and memory system is a Direct memory access engine that can operate between any of its peripherals and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which enables very high throughput for applications that can take advantage of it such as real-time standard-definition (D1) video encoding and decoding.

Micro-controller Features The Blackfin architecture contains a number of attributes commonly found on microprocessors and micro-controllers. These features allow Blackfin to efficiently and securely run many commercial and open-source operating systems.

Memory Protection Unit : All Blackfin processors contain a Memory Protection Unit (MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support many full-featured operating systems, RTOSs and kernels like ThreadX, µC/OS-II, or (noMMU) Linux. The Blackfin MPU does not provide address translation like a traditional Memory_management_unit (MMU) thus it does not support virtual memory or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or QNX. Just to confuse everyone, in most of the Blackfin documentation, the MPU is referred to as a MMU.

User/Supervisor Modes : Blackfin supports three run-time modes : supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc) an exception will be thrown and the kernel will then be able to shut down the offending thread/process.

Variable-Length, RISC-Like Instruction Set : Blackfin supports 16, 32 and 64-bit instructions. Commonly-used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32 and 64-bit opcodes. This variable length opcode encoding allows Blackfin to achieve good code density equivalent to modern micro-processor architectures.

Media Processing Features The Blackfin instruction set contains media processing extensions to help accelerate pixel processing operations commonly used in video and image compression/decompression algorithms.

Peripherals Blackfin processors contain a wide array of connectivity peripherals.

USB_OTG
ATAPI
MXVR : a MOST (Media Oriented Systems Transport) Network Interface Controller. MOST is a registered trademark of SMSC.
Parallel Peripheral Interface) : A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 65MHz and can be configured from 8 to 16-bits wide.
SPORT : A synchronous, high speed serial port that can support TDM, I2S and a number of other configurable framing modes for connection to ADCs, DACs, other processors, FPGAs, etc.
Controller Area Network : A wide-area, low-speed serial bus that is fairly popular in automotive and industrial electronics.
UART (Universal Asynchronous Receiver Transmitter) : allows for bi-directional communication with RS232 devices (PCs, modems, PC peripherals, etc), MIDI devices, IRDA devices.
Serial Peripheral Interface : A staple of (relatively) high-speed embedded electronics.
I²C (also known as TWI (two-wire interface)) : A lower speed, shared serial bus.

Because all of the peripheral control registers are memory-mapped I/O in the normal address space, they are quite easy to set-up.

Development Tools Software ADI provides its own software development toolchain, CROSSCORE (VisualDSP++), but other options are also available, such as Green Hills Software's MULTI IDE, the GNU GNU Compiler Collection Toolchain for the Blackfin processor family, or National Instruments' LabVIEW Embedded Module.

Blackfin Software Development Kit (SDK) The Analog Devices Blackfin SDK contains free applications software with source code, utilities information and tools that allow you to develop Blackfin processor based applications. The software can be used as a framework, or as examples of how to use certain aspects and peripherals, in conjunction with an ADI Blackfin processor.

Supported Operating Systems, RTOSs & Kernels Blackfin supports numerous commercial and open-source operating systems.

{| class="wikitable"|+OS/RTOS/Kernels on Blackfin!Title || Type!! Home Page !!Comments|-|Uclinux || Open-Source/GPL ] || Commercial || http://www.rtos.com |||-|Nucleus_RTOS || Commercial || http://www.mentor.com |||-|Fusion || Commercial || http://www.unicoi.com/fusion_rtos/rtos_blackfin.htm |||-|Micro_C/OS_II || Commercial/Source Available || http://www.micrium.com/ |||-|velOSity_(operating_system) || Commercial || http://www.ghs.com|||-|integrity_(operating_system) || Commercial || http://www.ghs.com|||-|RTEMS ] || http://www.rtems.com/ |||-|T2 SDE ] || http://www.t2-project.org/architectures/blackfin.html |||-|VDK|| Commercial || http://www.analog.com/blackfin || ADI's real-time kernel. Ships with VisualDSP++.|-|}

See also

Super Harvard Architecture Single-Chip Computer
TigerSHARC

External links

Blackfin processor website
Blackfin Forum, a web community for users of the processors
uClinux for Blackfin, various open source projects for Blackfin
Express Logic RTOS manufacturer for various processors, including Blackfin.
Cambridge Signal Processing Computer modules based on the Blackfin.
UoC ECE-ADI-Project University of Calgary project homepages (links to other university projects and helpful material).
Bluetechnix Blackfin Modules Company providing smallest Blackfin based Core Modules
PEEDI, JTAG Emulator and Flash Programmer for Blackfin

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